Waveform generator for use in iq modulation

ABSTRACT

A waveform generator for use in IQ modulation in a wireless cellular device having an FM waveform generator ( 104 ) that is programmable to generate a desired FM frequency deviation; a digital accumulator ( 108, 110, 112 ) to provide phase generation.  
     First and second look-up tables  114  and  116  use the 6 MSBs and the 6 LSBs of 12-bit digital accumulator values to look up phase-space values that are combined in complex multipliers ( 130, 140 ), which are re-used from other parts of the circuit.  
     This provides the following advantage(s):  
     Support of both FM and I/Q modulation techniques for constant envelope modulation; low cost implementation; and flexibility to address multimode systems.

FIELD OF THE INVENTION

[0001] This invention relates to waveform generators for use in IQ(In-phase, Quadrature-phase) modulation. IQ modulators are used in interalia circuitry of wireless communications transceivers, such as mobiletelephones.

BACKGROUND OF THE INVENTION

[0002] In the field of this invention it is known to provide either IQmodulation or FM (Frequency Modulation) direct PLL (Phase Locked Loop)modulation as separate types of modulation techniques, each with its owndedicated circuitry.

[0003] However, this approach has the disadvantage(s) that if a singlecircuit is desired to provide multi-mode operation (i.e., operation inany of a desired range of communications protocols requiring differentmodulation schemes, e.g., GSM (General System for Mobilecommunications), Bluetooth, HomeRF, AMPS (Advanced Mobile PhoneService), TETRA (Terrestrial Trunked Radio), CDMA (Code DivisionMultiple Access), etc.), the need to provide multiple modulationcircuits for multiple possible modulation schemes significantlyincreases cost and power consumption.

[0004] As an example, if a GSM-only radio mode is required, then FMmodulation would be used. If GSM and EDGE modulation are required wherean IQ modulator is needed for EDGE, then GSM modulation through an IQmodulator rather FM modulator would be used, assuming that the RF IQmodulator meets the receiver noise requirements to avoid using a TXfilter or duplexer.

[0005] A need therefore exists for having an FM modulation and/or an IQmodulation on the same transceiver circuit, and for a waveform generatorfor use in IQ modulation wherein the abovementioned disadvantage(s) maybe alleviated.

STATEMENT OF INVENTION

[0006] In accordance with the present invention there is provided awaveform generator for use in IQ modulation as claimed in claim 1.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] One waveform generator circuit for use in an IQ modulator ofcellular radio transceiver incorporating the present invention will nowbe described, by way of example only, with reference to the accompanyingdrawing(s), in which:

[0008]FIG. 1A and FIG. 1B show block schematic diagrams of the frequencymodulation and IQ modulation sections of the waveform generator circuit;and

[0009]FIG. 2 shows a block schematic diagram illustrating waveformscaling performed in the circuit;

[0010]FIG. 3 shows a first cascaded PLL arrangement, incorporating thewaveform generator circuit of FIG. 1, for direct TX modulation to removeany remodulation effect; and

[0011]FIG. 4 shows a second cascaded PLL arrangement, incorporating thewaveform generator circuit of FIG. 1, for reducing close-in noise.

DESCRIPTION OF PREFERRED EMBODIMENT(S)

[0012] Referring firstly to FIG. 1, the FM and IQ modulation sections inthe transmit section of a cellular radio transceiver circuit 100 includea phase mapping circuit 102 (e.g., in GSM, a differential encoder) forreceiving a transmit signal SDTX (comprising serial bits to betransmitted that are received from a host processor unit—not shown). Theoutput of the phase mapping circuit 102 is connected to a programmableFM pre-distortion waveform generator 104, which receives data inputs X1d, X2 d and X3 d from a look-up table (not shown) and receives anoversampled clock signal from a clock signal generator (also not shown).The FM waveform generator 104 produces an 18-bit output that is appliedvia a divider 106 (which divides by a factor of 2⁹) to a digitalaccumulator constituted by an adder 108, a register 110 and a rounder112. The register 110 is clocked by the same oversampled clock signal asthe FM waveform generator 104 and is arranged to be cleared on a risingedge of a DMCS signal (a trigerring signal, to start the transmitmodulation, whose duration is nearly equal to the transmit burst length;this signal is typically received from a timing unit located in the hostprocessor—not shown), and the output of the register 110 is fed back toan input of the adder 108.

[0013] The 21-bit output of the register 110 is rounded in a rounder 112to 12-bits, which are split into two parallel data streams comprisingrespectively the six most significant bits and the six least significantbits of the rounded accumulator value. The six most significant bits areapplied to a 16-word MSB Phase Look-Up table 114 to produce pairs of11-bit values representative of the cosine and sine values (cos_((φMSB))and sin_((φMSB)) respectively) of points in phase-space given by theinput six most significant bits. Similarly, the six least significantbits are applied to a 64-word LSB Phase Look-Up table 116 to producepairs of 11-bit values representative of the cosine and sine values(cos_((φLSB)) and sin_((φLSB)) respectively) of points in phase spacegiven by the input six least significant bits. It will be understoodthat splitting the 12-bit rounded accumulator signal into its six mostsignificant bits and its six least significant bits requires therespective look-up tables 114 and 116 to have sizes of 16 and 64 wordsrespectively, and that the resultant combined size of 80 words is theminimum size, and so allows minimization of total integrated circuitarea occupied by these lookup tables.

[0014] It is also possible to split the 12-bit rounded accumulatorsignal into its seven most significant bits and five least significantbits, requiring look-up tables 114 and 116 to have sizes of 32 and 32words respectively, assuming that a quarter table length is stored intable 114 (by taking advantage of the symmetry of the sine and cosinefunction).

[0015] Also, the least significant bits look-up table 116 that storescos_((φLSB)) and sin_((φLSB)) of the phase that corresponds to _(φLSB)can be approximated to 1 and _(φLSB) respectively since _(φLSB) is verysmall, in which case the look-up table 116 can be removed.

[0016] Referring now also to FIG. 1B, the MSB and LSB sine and cosinevalues produced from the look-up tables 114 and 116 are combined incomplex multiplier arrangements 130 and 140 in-phase (I) andquadrature-phase (Q) modulation values for application to respectivedigital/analog (D/A) converters (not shown) for subsequent transmission.

[0017] The complex multiplier arrangement 130 has a multiplier 132 thatreceives the most significant bit cosine value (cos_((φMSB))) from thelook-up table 114 and the least significant bit cosine value(cos_((φLSB))) from the look-up table 116 and produces a multipliedoutput to an adder 134. The complex multiplier arrangement 130 also hasa multiplier 136 that receives the most significant bit sine value(sin_((φMSB))) from the look-up table 114 and the least significant bitsine value (sin_((φLSB))) from the look-up table 116 and produces amultiplied output to the adder 134. The adder 134 produces a 22-bitoutput, which is rounded to 10 bits in a rounder 138, and this 10-bitrounded value is applied to an in-phase (I) D/A converter (not shown)for transmission. It will thus be understood that the rounded value (I)at the output of the complex multiplier arrangement 130 is given by:

I=cos_((φLSB+φMSB)).

[0018] The complex multiplier arrangement 140 has a multiplier 142 thatreceives the most significant bit cosine value (cos_((φMSB))) from thelook-up table 114 and the least significant bit sine value(sin_((φLSB))) from the look-up table 116 and produces a multipliedoutput to an adder 144. The complex multiplier arrangement 140 also hasa multiplier 146 that receives the most significant bit sine value(sin_((φMSB))) from the look-up table 114 and the least significant bitcosine value (cos_((φLSB))) from the look-up table 116 and produces amultiplied output to the adder 144. The adder 144 produces a 22-bitoutput, which is rounded to 10 bits in a rounder 148, and this 10-bitrounded value is applied to a quadrature-phase (Q) D/A converter (notshown) for transmission. It will thus be understood that the roundedvalue (Q) at the output of the complex multiplier arrangement 140 isgiven by:

Q=sin_((φLSB+φMSB)).

[0019] It will further be understood that the complex multipliers 130and 140 need not be provided exclusively for the use described above fortransmission, but instead IQ multipliers provided elsewhere in thecircuit (for example, in the receiver section, or in the transmitsection where pulse shaping filtering occurs using Finite ImpulseResponse (FIR) circuitry) can be re-used for this purpose.

[0020] Referring now also to FIG. 2, in the transceiver circuit 100 theFM waveform generator 104 is arranged to drive a main receivephase-locked-loop (PLL) 150 in conjunction with a receivevoltage-controlled oscillator (RX VCO) 152. The RX VCO signal is used todrive a near-unity transmission PLL loop (of known type) 160 inconjunction with a transmit voltage-controlled oscillator (TX VCO) 162.The TX VCO signal is used to drive an IQ RF modulator section 170, whichreceives the I and Q signals produced by the complex multipliers 130 and140 described above in relation to FIG. 1.

[0021] The cascade of two PLLs, i.e. the PLL 150 and the PLL 160, isused for direct TX modulation to remove any remodulation effect of thetransmit VCO where the TX VCO 162 is within a loop PLL which has largebandwidth since it operates with a high reference clock derived from 152and uses a near unity divider, while the reference clock 152 is derivedfrom a narrow loop PLL.

[0022] It will be understood that FM modulation may be achieved by useof the first phase-locked loop 150 and the second transmit loop 160,with the in-phase and quadrature-phase inputs of the IQ modulator 170set to their maximum values.

[0023] Referring now also to FIG. 3, it is possible to pass any FMmodulation through the near-unity transmit loop 160 (as is known for GSMmodulation) by modulating the first PLL 150 through noise shapingcircuitry and also scale the FM frequency deviation by reprogramming thewaveform generator coefficients to compensate the multiplication factorof the near-unity divider 161 in the transmit loop 160, where the outputfrequency can be expressed as:

FTX=fxtal*NUD*NL since fTX=fref*NUD, where NUD is the near unity value.

[0024] Referring also to FIG. 4, in order to reduce the close-in noiseof the arrangement shown in FIG. 3, the feedback point of TX VCO 162 iscoupled not only at the near-unity transmit loop, but also at the NLdivider in 150, since the noise source effect on phasecomparator/frequency steering and charge pump 163 of the PLL 160 isreduced by having the loop PLL 160 encompass within the PLL 150 withoutcompromising stability since loop PLL 160 is of wider bandwidth thanloop PLL 150. By reducing the overall close-in noise of the cascadedPLLs, it is possible then to pass on FM modulation with low close-innoise.

[0025] This modulation is passed to the TX VCO 162, which avoids thenusing an RF switch.

[0026] It will, of course, be appreciated that the present invention andthe above-described embodiment(s) lend themselves readily to use inintegrated circuit form, embodied in an arrangement of one or moreintegrated circuits, where many of the invention's advantages assumegreater significance.

[0027] It will be understood that the waveform generator for use in IQmodulation described above provides the following advantages:

[0028] It supports both FM and I/Q modulation techniques for constantenvelope modulation

[0029] It provides a low cost implementation

[0030] It provides flexibility to address multimode systems

[0031] It allows FM modulation through cascaded PLLs that are used inDirect Launch I/Q systems for remodulation cancellation.

1. A waveform generator (100) for use in IQ modulation, comprising: digital frequency modulation waveform generator means (104) for generating digital values representative of any of a predetermined range of desired frequency modulation schemes; and digital accumulator means (108, 110, 112) for accumulating digital values produced by said digital frequency modulation waveform generator means.
 2. The waveform generator according to claim 1 further comprising: first look-up means for receiving only a most significant group of bits produced by the digital accumulator means and for looking up in a first look-up table (114) phase-space values (cos_((φMSB)), sin_((φMSB))) associated with the received most significant group of bits; second look-up means for receiving only a least significant group of bits produced by the digital accumulator means and for looking up in a second look-up table (116) phase-space values (cos_((φLSB)), sin_((φLSB))) associated with the received least significant group of bits; and combining means (130, 140) for combining the phase-space values produced by the first and second look-up means to produce in-phase and quadrature-phase values (I, Q) for transmission modulation.
 3. The waveform generator according to claim 2 wherein said most significant group of bits and said least significant group of bits each comprise substantially half the number of bits in the values produced by said digital accumulator means.
 4. The waveform generator according to claim 2 or 3 wherein: said values produced by said digital accumulator means comprise 12 bits; said most significant group of bits comprises 7 bits and said least significant group of bits comprises 5 bits; said first look-up table comprises 32 words; and said second look-up table comprises 32 words.
 5. The Waveform generator according to claim 1 wherein said values produced by the digital accumulator means comprise 12 bits, and wherein the waveform generator further comprises: look-up means for receiving only the most significant 7 bits of values produced by the digital accumulator means and for looking up in a first look-up table (114) phase-space values (cos_((φMSB)), sin_((φMSB))) associated with the received most significant 7 bits; approximating means for receiving only the least significant 5 bits produced by the digital accumulator means and for deriving therefrom phase-space values (cos_((φLSB)), sin_((φLSB))) associated therewith by approximating to unity a cosine value associated therewith and approximating to the value of the least significant 5 bits a sine value associated therewith; and combining means (130, 140) for combining the phase-space values produced by the look-up means and the approximating means to produce in-phase and quadrature-phase values (I, Q) for transmission modulation.
 6. The waveform generator according to claim 2, 3 or 4 or 5 wherein said combining means comprises: first multiplier means (132 or 142) for multiplying a first pair of said phase-space values to produce a first multiplied value; second multiplier means (136 or 146) for multiplying a second pair of said phase-space values to produce a second multiplied value; and summing means (134 or 144) for summing said first multiplied value and second multiplied value.
 7. The waveform generator according to claim 2, 3, 4 or 5 or 6 wherein the combining means comprises means arranged for other uses.
 8. An integrated circuit transceiver arrangement for use in a wireless communication device and comprising a waveform generator according to any preceding claim.
 9. A wireless communication device containing a waveform generator according to any one of claims 1-6.
 10. A transceiver for use in a wireless communication device comprising: waveform generator means (100) for producing in-phase and quadrature-phase signals (I, Q) for digital frequency modulation; a first phase-locked-loop (150) having a receive voltage-controlled oscillator (152); a second transmit loop (160) having a transmit voltage-controlled oscillator (162) and receiving a signal from said receive voltage-controlled oscillator; and IQ modulator means (170) for receiving said in-phase and quadrature-phase signals from said waveform generator means and for producing an IQ modulated signal for transmission.
 11. The transceiver according to claim 10, wherein the digital frequency modulation is scaled to compensate for frequency multiplication in the second transmit loop
 160. 12. The transceiver according to claim 10 or 11, wherein the output of the second transmit loop 160 is also used as a feedback point to a divider in the first phase-locked loop
 150. 13. The transceiver according to claim 10, 11 or 12, arranged for FM modulation by use of the first phase-locked loop (150) and the second transmit loop (160), with the in-phase and quadrature-phase inputs of the IQ modulator 170 being arranged to receive signals at their maximum values.
 14. A wireless communication device containing a transceiver according to claim 10, 11, 12 or
 13. 